The present invention relates to a master slice type semiconductor integrated circuit device, specifically, a gate array. More particularly, the invention relates to a novel gate arrangement of such a device.
FIG. 1 shows the arrangement of a conventional semiconductor integrated circuit device of a type in which a unit cell 30 (surrounded by a dotted line) includes gate regions 31a and 31b and source or grain regions 32a and 32b which constitute MOS transistors. The number of MOS transistors in the unit cell 30 can be selected arbitrarily. That is, if the unit cell 30 is to be constituted with four pairs of MOS transistors as shown, adjacent gate regions 311a and 311b, which are essentially identical to the gate regions 31a and 31b, are connected to a positive source potential and a ground potential, respectively, to cut off MOS transistors having and gate regions 311a and 311b, and to thereby isolate the unit cell 30 from the surrounding regions.
FIG. 2 shows an arrangement of a four-input NOR gate in which reference numerals 41 and 42 depict aluminum wiring in first and second layers, respectively. Input signals IN1 to IN4 are supplied through the aluminum wiring 42 in the second layer to gate electrodes 31a of p channel MOS transistors and gate electrodes 31b of n channel MOS transistors, and an output signal is obtained at an output terminal OUT through the aluminum wiring 42. Electrical connection between the MOS transistors of the four-input NOR gate is realized by the aluminum wiring 41 in the first layer. Reference numeral 51 depicts contact holes for connection between the aluminum wiring 41 in the first layer and p or n type source or drain regions 32a and 32b formed on the surface of a semiconductor substrate, 52 connection points between the aluminum wiring 42 in the second layer and the gate regions 31a and 31b, and 53 a connection point between the aluminum wirings 41 and 42.
In the conventional semiconductor device constructed as above, only p and n channel MOS transistors each of a certain constant size can be formed. This may be acceptable when the circuit device is used as a digital circuit component. However, for use as an analog circuit component, it is desirable to have variously sized MOS transistors. In order to realize such variously sized MOS transistors in the conventional circuit device, it may be possible to connect like-sized MOS transistors in series or in parallel. In the latter case, however, the required area of the circuit device becomes too large. In addition thereto, there is a problem of undesired current flows.